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74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

Download the 74LS112A datasheet PDF (74LS112 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for dual negative-edge-triggered master-slave j-k flip-flop.

Description

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.

The J and K data is processed by the flip-flop on the falling edge of the clock pulse.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74LS112_FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Full PDF Text Transcription

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DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times are not violated.
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