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Fairchild Semiconductor Electronic Components Datasheet

74LS221 Datasheet

Dual Non-Retriggerable One-Shot

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August 1986
Revised April 2000
DM74LS221 Dual Non-Retriggerable One-Shot
with Clear and Complementary Outputs
General Description
The DM74LS221 is a dual monostable multivibrator with
Schmitt-trigger input. Each device has three inputs permit-
ting the choice of either leading-edge or trailing-edge trig-
gering. Pin (A) is an active-LOW trigger transition input and
pin (B) is an active-HIGH transition Schmitt-trigger input
that allows jitter free triggering for inputs with transition
rates as slow as 1 volt/second. This provides the input with
excellent noise immunity. Additionally an internal latching
circuit at the input stage also provides a high immunity to
VCC noise. The clear (CLR) input can terminate the output
pulse at a predetermined time independent of the timing
components. This (CLR) input also serves as a trigger
input when it is pulsed with a low level pulse transition
( ). To obtain the best and trouble free operation from
this device please read operating rules as well as the Fair-
child Semiconductor one-shot application notes carefully
and observe recommendations.
Features
s A dual, highly stable one-shot
s Compensated for VCC and temperature variations
s Pin-out identical to DM74LS123 (Note 1)
s Output pulse width range from 30 ns to 70 seconds
s Hysteresis provided at (B) input for added noise
immunity
s Direct reset terminates output pulse
s Triggerable from CLEAR input
s DTL, TTL compatible
s Input clamp diodes
Note 1: The pin-out is identical to DM74LS123 but, functionally it is not;
refer to Operating Rules #10 in this datasheet.
Ordering Code:
Order Number Package Number
Package Description
DM74LS221M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS221SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS221N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
CLEAR
A
B
Q
Q
L XXLH
X HXLH
X
H
H
(Note 2)
X
L
L
L
H
H
L
H
H = HIGH Logic Level
L = LOW Logic Level
X = Can Be Either LOW or HIGH
↑ = Positive Going Transition
↓ = Negative Going Transition
= A Positive Pulse
= A Negative Pulse
Note 2: This mode of triggering requires first the B input be set from a
LOW-to-HIGH level while the CLEAR input is maintained at logic LOW
level. Then with the B input at logic HIGH level, the CLEAR input whose
positive transition from LOW-to-HIGH will trigger an output pulse.
© 2000 Fairchild Semiconductor Corporation DS006409
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

74LS221 Datasheet

Dual Non-Retriggerable One-Shot

No Preview Available !

Functional Description
The basic output pulse width is determined by selection of
an external resistor (RX) and capacitor (CX). Once trig-
gered, the basic pulse width is independent of further input
transitions and is a function of the timing components, or it
may be reduced or terminated by use of the active low
CLEAR input. Stable output pulse width ranging from 30 ns
to 70 seconds is readily obtainable.
Operating Rules
1. An external resistor (RX) and an external capacitor
(CX) are required for proper operation. The value of CX
may vary from 0 to approximately 1000 µF. For small
time constants high-grade mica, glass, polypropylene,
polycarbonate, or polystyrene material capacitor may
be used. For large time constants use tantalum or spe-
cial aluminum capacitors. If timing capacitor has leak-
ages approaching 100 nA or if stray capacitance from
either terminal to ground is greater than 50 pF the tim-
ing equations may not represent the pulse width the
device generates.
2. When an electrolytic capacitor is used for CX a switch-
ing diode is often required for standard TTL one-shots
to prevent high inverse leakage current. This switching
diode is not needed for the DM74LS221 one-shot and
should not be used.
Furthermore, if a polarized timing capacitor is used on
the DM74LS221, the positive side of the capacitor
should be connected to the CEXTpin (Figure 1).
3. For CX >> 1000 pF, the output pulse width (tW) is
defined as follows:
tW = KRX CX
where [RX is in k]
[CX is in pF]
[tW is in ns]
K Ln2 = 0.70
4. The multiplicative factor K is plotted as a function of CX
for design considerations: (See Figure 4).
5. For CX < 1000 pF see Figure 3 for tW vs. CX family
curves with RX as a parameter.
6. To obtain variable pulse widths by remote trimming,
the following circuit is recommended: (See Figure 2).
7. Output pulse width versus VCC and temperatures: Fig-
ure 5 depicts the relationship between pulse width vari-
ation versus VCC. Figure 6 depicts pulse width variation
versus temperatures.
8. Duty cycle is defined as tW/T × 100 in percentage, if it
goes above 50% the output pulse width will become
shorter. If the duty cycle varies between LOW and
HIGH values, this causes output pulse width to vary, or
jitter (a function of the REXT only). To reduce jitter, REXT
should be as large as possible, for example, with
REXT = 100k jitter is not appreciable until the duty cycle
approaches 90%.
9. Under any operating condition CX and RX must be kept
as close to the one-shot device pins as possible to min-
imize stray capacitance, to reduce noise pick-up, and
to reduce I-R and Ldi/dt voltage developed along their
connecting paths. If the lead length from CX to pins (6)
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations.
A non-inductive and low capacitive path is necessary to
ensure complete discharge of CX in each cycle of its
operation so that the output pulse width will be accu-
rate.
10. Although the DM74LS221's pin-out is identical to the
DM74LS123 it should be remembered that they are not
functionally identical. The DM74LS123 is a retrigger-
able device such that the output is dependent upon the
input transitions when its output Qis at the High
state. Furthermore, it is recommended for the
DM74LS123 to externally ground the CEXT pin for
improved system performance. However, this pin on
the DM74LS221 is not an internal connection to the
device ground. Hence, if substitution of an DM74LS221
onto an DM74LS123 design layout where the CEXT pin
is wired to the ground, the device will not function.
11. VCC and ground wiring should conform to good high-
frequency standards and practices so that switching
transients on the VCC and ground return leads do not
cause interaction between one-shots. A 0.01 µF to 0.10
µF bypass capacitor (disk ceramic or monolithic type)
from VCC to ground is necessary on each device. Fur-
thermore, the bypass capacitor should be located as
close to the VCC-pin as space permits.
www.fairchildsemi.com
2


Part Number 74LS221
Description Dual Non-Retriggerable One-Shot
Maker Fairchild Semiconductor
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74LS221 Datasheet PDF






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