74LVQ138 Datasheet | Fairchild Semiconductor

74LVQ138 Low Voltage 1-of-8 Decoder/Demultiplexer May 1998 74LVQ138 Low Voltage 1-of-8 Decoder/Demultiplexer General Description The LVQ138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LVQ138 devices or a 1-of-32 decoder using four LVQ138 devices and one inverter. Features n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Guaranteed incident wave switching into 75Ω n 4 k V minimum ESD immunity n Demultiplexing capability n Multiple input enable for each expansion n Active LOW mutually exclusive outputs Ordering Code: Order Number 74LVQ138SC 74LVQ138SJ Package Number M16A M16D Package Description 16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC 16-Lead Molded Small Outline Package, SOIC EIAJ Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Pin Assignment for SOIC JEDEC and EIAJ DS011350-1 IEEE/IEC DS011350-2 Pin Descriptions Pin Names A0- A2 E1- E2 DS011350-4 Description Address Inputs Enable Inputs Enable Input Outputs E3 O0- O7 © 1998 Fairchild Semiconductor Corporation DS011350 .fairchildsemi. Functional Description The LVQ138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted inputs (A0, A1, A2) and, when enabled, provides eight mutually exclusive active-LOW outputs (O0- O7). The LVQ138 Features three Enable inputs, two active-LOW (E1, E2) and one active-HIGH (E3). All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four LVQ138 devices and one inverter (see Figure 1). The LVQ138 can be used as an...