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Fairchild Semiconductor Electronic Components Datasheet

74LVTH125 Datasheet

Low Voltage Quad Buffer with 3-STATE Outputs

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74LVTH125 pdf
October 1998
Revised January 1999
74LVTH125
Low Voltage Quad Buffer with 3-STATE Outputs
General Description
The LVTH125 contains four independent non-inverting buff-
ers with 3-STATE outputs.
These buffers are designed for low-voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH125 is fabricated with
an advanced BiCMOS technology to achieve high speed
operation similar to 5V ABT while maintaining a low power
dissipation.
Features
s Input and output interface capability to systems at 5V
VCC
s Bus-Hold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free bus
loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 125
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH125M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
74LVTH125SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH125MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
An, Bn
On
Inputs
3-STATE Outputs
Truth Table
Inputs
An
L
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
Bn
L
H
X
Output
On
L
H
Z
© 1999 Fairchild Semiconductor Corporation DS012011.prf
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

74LVTH125 Datasheet

Low Voltage Quad Buffer with 3-STATE Outputs

No Preview Available !

74LVTH125 pdf
Absolute Maximum Ratings(Note 1)
Symbol
VCC
VI
VO
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
IIK DC Input Diode Current
IOK DC Output Diode Current
IO DC Output Current
ICC
IGND
TSTG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
0.5 to +4.6
0.5 to +7.0
0.5 to +7.0
0.5 to +7.0
50
50
64
128
±64
±128
65 to +150
Conditions
Output in 3-STATE
Output in HIGH or LOW State (Note 2)
VI < GND
VO < GND
VO > VCC Output at HIGH State
VO > VCC Output at LOW State
Units
V
V
V
mA
mA
mA
mA
mA
°C
Recommended Operating Conditions
Symbol
Parameter
Min Max Units
VCC Supply Voltage
2.7 3.6
V
VI Input Voltage
0 5.5
V
IOH HIGH Level Output Current
32 mA
IOL LOW Level Output Current
64 mA
TA Free-Air Operating Temperature
40 85
°C
t/V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0 10 ns/V
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 2: IO Absolute Maximum Rating must be observed.
www.fairchildsemi.com
2


Part Number 74LVTH125
Description Low Voltage Quad Buffer with 3-STATE Outputs
Maker Fairchild Semiconductor
Total Page 6 Pages
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