74LVTH16543 Datasheet | Fairchild Semiconductor

74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs January 2000 Revised January 2000 74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs General Description The LVTH16543 16-bit transceiver contains two sets of Dtype latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Each byte has separate control inputs, which can be shorted together for full 16-bit operation. The LVTH16543 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16543 is fabricated with an advanced Bi CMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. Features s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink - 32 m A/+64 m A s Functionally patible with the 74 series 16543 s Latch-up performance exceeds 500 m A Ordering Code: Order Number 74LVTH16543MEA 74LVTH16543MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2000 Fairchild Semiconductor Corporation DS012449 .fairchildsemi. Connection Diagram Pin Descriptions Pin Names OEABn OEBAn CEABn CEBAn LEABn LEBAn A0- A15 Description A-to-B Output Enable Input...