74LVX573 Datasheet | Fairchild Semiconductor

Description The LVX573 is a high-speed octal latch with buffered mon Latch Enable (LE) and buffered mon Output Enable (OE) inputs. The LVX573 is functionally identical to the LVX373 but with inputs and outputs on opposite sides of the package. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems. Features s Input voltage translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Order Number Package Number Package Description 74LVX573M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVX573SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0- D7 LE OE O0- O7 Description Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs © 2005 Fairchild Semiconductor Corporation DS011616 .fairchildsemi. Functional Description The LVX573 contains eight D-type latches. When the enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Truth Table Inputs Outputs On...