Datasheet4U Logo Datasheet4U.com

74S112 - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

Product Overview

📥 Download Datasheet

Datasheet preview – 74S112

Datasheet Details

Part number 74S112
Manufacturer Fairchild Semiconductor
File Size 42.41 KB
Description Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
Datasheet download datasheet 74S112 Datasheet
Additional preview pages of the 74S112 datasheet.

Product details

Description

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.

📁 Similar Datasheet

  • 74S10 - STTL type three 3-input NAND gate (TW)
  • 74S133 - 13-Input NAND Gate (SYC)
  • 74S134 - 12-INPUT POSITIVE-NAND GATES (Fairchild)
  • 74S134 - 12-INPUT POSITIVE-NAND GATES (Signetics)
  • 74S135 - Quad Exclusive OR/NOR Gate (Fairchild)
  • 74S135 - Quad Exclusive OR/NOR Gate (Signetics)
  • 74S140 - Dual 4-Input NSND Line Driver (National Semiconductor)
  • 74S15 - STTL type three 3-input AND gate (TW)
Other Datasheets by Fairchild Semiconductor
  • 74S138 - Decoder/Demultiplexer
  • 74S139 - Decoder/Demultiplexer
  • 74S140 - Dual 4-Input NSND Line Driver
  • 74S153 - Dual 1-of-4 Line Data Selector/Multiplexer
  • 74S157 - Quad 1 of 2 Line Data Selectors/Multiplexers
  • 74S158 - Quad 1 of 2 Line Data Selectors/Multiplexers
Published: |