Datasheet Details
| Part number | 74S112 |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 42.41 KB |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
| Download | 74S112 Download (PDF) |
|
|
| Part number | 74S112 |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 42.41 KB |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
| Download | 74S112 Download (PDF) |
|
|
|
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.
The J and K data is processed by the flip-flops on the falling edge of the clock pulse.
The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse.
DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset,.
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