Datasheet Summary
DM74S10 Triple 3-Input NAND Gate
August 1986 Revised April 2000
DM74S10 Triple 3-Input NAND Gate
General Description
This device contains three independent gates each of which performs the logic NAND function.
Ordering Code:
Order Number Package Number
Package Description
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Y = ABC
Inputs AB XX XL LX HH
H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level
C L X X H
Output Y H H H L
© 2000 Fairchild Semiconductor Corporation DS006446
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