DM74S112 datasheet by Fairchild (now onsemi).
| Part number | DM74S112 |
|---|---|
| Datasheet | DM74S112-FairchildSemiconductor.pdf |
| File Size | 42.46 KB |
| Manufacturer | Fairchild (now onsemi) |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
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This device contains two independent negative-edge-triggered J-K flip-flops with plementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse.
View all Fairchild (now onsemi) datasheets
| Part Number | Description |
|---|---|
| DM74S11 | Triple 3-Input AND Gate |
| DM74S10 | Triple 3-Input NAND Gate |
| DM74S133 | 13-Input NAND Gate |
| DM74S138 | Decoder/Demultiplexer |
| DM74S139 | Decoder/Demultiplexer |
| DM74S140 | Dual 4-Input NAND 50ohm Line Driver |
| DM74S151 | 1-of-8 Data Selector/Multiplexer |
| DM74S153 | Dual 1-of-4 Line Data Selector/Multiplexer |
| DM74S157 | Quad 1 of 2 Line Data Selector/Multiplexer |
| DM74S158 | Quad 1 of 2 Line Data Selector/Multiplexer |
