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DM74S10 - Triple 3-Input NAND Gate

General Description

This device contains three independent gates each of which performs the logic NAND function.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DM74S10 Triple 3-Input NAND Gate August 1986 Revised April 2000 DM74S10 Triple 3-Input NAND Gate General Description This device contains three independent gates each of which performs the logic NAND function. Ordering Code: Order Number Package Number Package Description DM74S10 N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Function Table Y = ABC Inputs AB XX XL LX HH H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level C L X X H Output Y H H H L © 2000 Fairchild Semiconductor Corporation DS006446 www.fairchildsemi.com DM74S10 Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.