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Fairchild Semiconductor Electronic Components Datasheet

DM74S112 Datasheet

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

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August 1986
Revised April 2000
DM74S112
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. Data on the J and
K inputs can be changed while the clock is HIGH or LOW
without affecting the outputs as long as setup and hold
times are not violated. A low logic level on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM74S112
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CLK J K
Q
Q
L H X XX H
L
HL
X XX L
H
LL
X X X H*
H*
HH
HH
HH
HH
LL
Q0
HL H
Q0
L
LH L
H
HH
Toggle
HH
H X X Q0
Q0
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
↓ = Negative going edge of pulse.
Q0 = The output logic level of Q before the indicated input conditions were
established.
* = This configuration is nonstable; that is, it will not persist when either the
preset and/or clear inputs return to its inactive (HIGH) level.
Toggle = Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
© 2000 Fairchild Semiconductor Corporation DS006459
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

DM74S112 Datasheet

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

No Preview Available !

Absolute Maximum Ratings(Note 1)
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range
65°C to +150°C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
Parameter
Min
VCC Supply Voltage
4.75
VIH HIGH Level Input Voltage
2
VIL LOW Level Input Voltage
IOH HIGH Level Output Current
IOL LOW Level Output Current
fCLK Clock Frequency (Note 2)
0
fCLK Clock Frequency (Note 3)
0
tW Pulse Width
Clock HIGH
6
(Note 2)
Clock LOW
6.5
Clear LOW
8
Preset LOW
8
tW Pulse Width
(Note 3)
Clock HIGH
Clock LOW
8
8
Clear LOW
10
Preset LOW
10
tSU Setup Time (Note 4)(Note 5)
7
tH Input Hold Time (Note 4)(Note 5)
0
TA Free Air Operating Temperature
0
Note 2: CL = 15 pF, RL = 280, TA = 25°C and VCC = 5V.
Note 3: CL = 50 pF, RL = 280, TA = 25°C and VCC = 5V.
Note 4: TA = 25°C and VCC = 5V.
Note 5: The symbol () indicates the falling edge at the clock pulse is used for reference.
Nom
5
125
80
Max
5.25
0.8
1
20
80
60
70
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
ns
°C
www.fairchildsemi.com
2


Part Number DM74S112
Description Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
Maker Fairchild Semiconductor
Total Page 4 Pages
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