DM74S112 Datasheet - Fairchild Semiconductor

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

DM74S112 General Description

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the neg.

DM74S112 Datasheet (42.46 KB)

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DM74S112

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Fairchild Semiconductor

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42.46 KB

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Dual negative-edge-triggered master-slave j-k flip-flop.
DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised April 2000 DM74S1.

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DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop Fairchild Semiconductor

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DM74S112 General Description

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