Datasheet4U Logo Datasheet4U.com

DM74S175 - Hex/Quad D Flip-Flop

Download the DM74S175 datasheet PDF. This datasheet also covers the DM74S174 variant, as both devices belong to the same hex/quad d flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop lo gic.

All h ave a d irect cle ar input, and the quad (DM74S175) versions feature complementary outputs from each flip-flop.

Key Features

  • s DM74S174 contain six flip-flops with single-rail outputs. s DM74S175 con tain fo ur fl ip-flops w ith do uble-rail outputs. s Buffered clock and direct clear inputs s Individual data input to each flip-flop s.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DM74S174-FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
DM74S132 Quad 2-Input Schmitt Trigger NAND Gate National Semiconductor
DM74S157 QUAD 1 OF 2 LINE DATA SELECTORS/MULTIPLEXERS National Semiconductor
DM74S158 QUAD 1 OF 2 LINE DATA SELECTORS/MULTIPLEXERS National Semiconductor
DM74S161 Synchronous 4-Bit Binary Counters National Semiconductor
DM74S163 Synchronous 4-Bit Binary Counters National Semiconductor

Other Datasheets by Fairchild (now onsemi)

Part Number Description
DM74S174 Hex/Quad D Flip-Flop
DM74S10 Triple 3-Input NAND Gate
DM74S11 Triple 3-Input AND Gate
DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
DM74S133 13-Input NAND Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DM74S174 • DM74S175 Hex/Quad D Flip-Flop with Clear August 1986 Revised April 2000 DM74S174 • DM74S175 Hex/Quad D Flip-Flop with Clear General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop lo gic. All h ave a d irect cle ar input, and the quad (DM74S175) versions feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either th e H IGH or LOW l evel, th e D i nput si gnal has no effect at the output.