datasheet4u.com

900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Fairchild Semiconductor Electronic Components Datasheet

FIN212AC Datasheet

12-Bit Serializer Deserializer

No Preview Available !

FIN212AC pdf
March 2007
FIN212AC
12-Bit Serializer Deserializer with Multiple Frequency Ranges
Features
Description
ƒ Low Power Consumption
ƒ Low Power, Proprietary, CTL I/O Serial Interface
The FIN212AC µSerDes is a low-power serializer /
deserializer optimized for use in cell phone displays and
camera paths. The device reduces a 12-bit data path to
ƒ Wide PLL Input Frequency Range
ƒ Wide Parallel Supply Voltage Range: 1.65 to 3.6V
four wires. The device can be configured as a serializer
or deserializer through the DIRI pin, minimizing
component types in the system. For camera
ƒ Low Power Core Operation: VDDS/A=2.5 to 3.6V
ƒ Built-in LV-CMOS Voltage Translation Capability
with no External Components
ƒ Adjustable Parallel Edge Rate
applications, an additional master clock can be passed
in the opposite direction of data flow.
The device utilizes Fairchild’s proprietary ultra-low
power, low-EMI technology. LV-CMOS parallel output
buffers have been implemented with slew rate control to
ƒ Operates as Serializer or Deserializer
ƒ Standby Power-Down Mode Support
adjust for capacitive loading and to minimize EMI. The
device also supports an ultra-low power-down mode for
conserving power in battery-operated applications
ƒ Built-in Differential Termination
Thewww.DataSheet4U.com device is available in a 5x5mm MLP package to
attach directly to a flex circuit, or in two choices of BGA,
Applications
where space constraints are a concern.
ƒ 8-Bit LCD Displays for Cell Phones
ƒ 8/10-Bit Cell Phone Camera Interface
ƒ 8-Bit LCD Displays for Printers
Related Application Notes
ƒ AN-5058 µSerDes™ Family Frequently Asked
Questions
ƒ AN-5061 µSerDes™ Layout Guidelines
Ordering Information
Order Number
Package
Pb-
Free
FIN212ACMLX MLP032A Yes
FIN212ACGFX BGA42A
Yes
FIN212ACBFX
BGA36A
(Preliminary)
Yes
Operating
Temperature
Range
-30 to 70°C
-30 to 70°C
-30 to 70°C
Package Description
32-Terminal Molded Leadless Package
(MLP), Quad, JEDEC MO-220, 5mm square
42-Ball Ultra Small-Scale Ball Grid Array
(USS-BGA), JEDEC MO-195, 3.5 x 4.5mm
wide, 0.5mm Ball Pitch
36-Ball Ultra Small Scale Ball Grid Array
(USS-BGA), JEDEC MO-xxx 2.5mm square,
0.4mm Ball Pitch
Packing
Method
Tape &
Reel
Tape &
Reel
Tape &
Reel
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

FIN212AC Datasheet

12-Bit Serializer Deserializer

No Preview Available !

FIN212AC pdf
Pin Definitions
Pin
I/O type
# of
Pins
Description of Signals
DP[1:12]
CMOS-I/O 12 LV-CMOS Parallel I/O. Direction controlled by DIRI pin.
CKREF
CMOS-IN 1 LV-CMOS clock input and PLL reference.
STROBE
CMOS-IN 1 LV-CMOS strobe input for latching data into the serializer.
CKP
DSO+(DSI-)(1)
DSO-(DSI+)
CMOS-
OUT
DIFF-I/O
1 LV-CMOS word clock output.
2
CTL Differential serial I/O data signals.(2)
DS(I)+: Positive signal of DS(I) pair; DS(I)-: Negative signal of DS(I) pair.
CKSI+, CKSI-
DIFF-IN
2
CTL Differential deserializer input bit clock.
CKSI+: Positive signal of CKSI pair; CKSI-: Negative signal of CKSI pair.
CKSO+,
CKSO-
CTL Differential serializer output bit clock.
DIFF-OUT 2 CKSO+: Positive signal of CKSO pair;
CKSO-: Negative signal of CKSO pair.
S0, S1
CMOS-IN
1
DIRI=1: signals are used to define frequency range for the PLL. DIRI=0:
Signals are used to define the edge rate of the deserializer parallel I/Os.
PLL0(PWS0) CMOS-IN
1
DIRI=1: PLL0 signal is used to divide or adjust the serial frequency.
DIRI=0: PWS0 signal is used to set the width of the CKP output pulse.
PLL1(PWS1) CMOS-IN
1
DIRI=1: PLL1 Signal is used to divide the serial frequency.
DIRI=0: PWS1 pin controls the output pulse width.
TEST /
(XTRM)
DIRI=1: TEST=0, Normal Operation. DIRI=0: Termination enable
CMOS_IN 1 functionality for deserializer. XTRM=0 Internal termination. XTRM=1
External termination required. Ground this pin for serializer.
CTL_ADJ
(GND)
CMOS_IN
1
Adjusts CTL drive for serializer. Ground this pin for deserializer.
DIRI
IN
1
LV-CMOS Control Input. Used to control direction of data flow: DIRI= “1”
Serializer, DIRI=“0” Deserializer
/DIRO
OUT
1 LV-CMOS Output. Inversion of DIRI in normal operation mode.
VDDP
Supply
1 Power supply for parallel I/O and translation circuitry.
VDDS
Supply
1 Power supply for core and serial I/O.
VDDA
Supply
1 Power supply for analog PLL circuitry.
GND
Supply
0
Ground center pad, ground D4, E3 and NCs for 42-ball BGA. Ground B5,
C2, C4 for 36-ball BGA.
Notes:
1. () Indicate deserializer functionality when DIRI=0.
2. The DS serial port pins are arranged such that when one device is rotated 180 degrees from the other device,
the serial connections properly align without the need for any traces or cable signals to cross. Other layout
orientations may require that traces or cables cross.
3. All unused LV-CMOS input signals should be connected to GND or VDDP. Signals can be connected directly to
the rail or through a resistor.
4. All unused LV-CMOS output signals should be allowed to float.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
2
www.fairchildsemi.com


Part Number FIN212AC
Description 12-Bit Serializer Deserializer
Maker Fairchild Semiconductor
Total Page 22 Pages
PDF Download
FIN212AC pdf
FIN212AC Datasheet PDF
[partsNo] view html
View PDF for Mobile








Similar Datasheet

1 FIN212AC 12-Bit Serializer Deserializer Fairchild Semiconductor
Fairchild Semiconductor
FIN212AC pdf





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy