FQD6P25 Datasheet | Fairchild Semiconductor

Description These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and mutation mode. These devices are well suited for high efficiency switching DC/DC converters. Features - - - - - - -4.7A, -250V, RDS(on) = 1.1Ω @VGS = -10 V Low gate charge ( typical 21 n C) Low Crss ( typical 20 p F) Fast switching 100% avalanche tested Improved dv/dt capability D G! G S ! D-PAK FQD Series I-PAK FQU Series ! Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed (Note 1) FQD6P25 / FQU6P25 -250 -4.7 -3.0 -18.8 ±30 (Note 2) (Note 1) (Note 1) (Note 3) Units V A A A V m J A m J V/ns W W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) - Power Dissipation (TC = 25°C) 540 -4.7 5.5 -5.5 2.5 55 0.44 -55 to +150 300 TJ, TSTG TL - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8from case for 5 seconds Thermal Characteristics Symbol RθJC RθJA RθJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient - Thermal Resistance, Junction-to-Ambient Typ ---Max 2.27 50 110 Units °CW °CW °CW - When mounted on the minimum pad size remended (PCB...