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MC100ES6139 - Clock Generation Chip

Description

Pin CLK(1), EN(1) MR(1) CLK(1) Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff ÷2/4 Outputs ECL Diff ÷4/5/6 Outputs ECL Freq.

Select Input ÷2/4 ECL Freq.

Select Input ÷4/5/6 ECL Freq.

Features

  • MC100ES6139 DT SUFFIX 20-LEAD TSSOP.

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Full PDF Text Transcription

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www.DataSheet4U.com Freescale Semiconductor Technical Data MC100ES6139 Rev 3, 06/2005 3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip The MC100ES6139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a singleended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01 µF capacitor.
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