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MC100ES6139 Clock Generation Chip

MC100ES6139 Description

www.DataSheet4U.com Freescale Semiconductor Technical Data MC100ES6139 Rev 3, 06/2005 3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip T.
Pin CLK(1), EN(1) MR(1) CLK(1) Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff ÷2/4 Outputs ECL Diff ÷4/.

MC100ES6139 Features

* MC100ES6139 DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-03 EJ SUFFIX 20-LEAD TSSOP PACKAGE Pb-FREE PACKAGE CASE 948E-03 ORDERING INFORMATION Device MC100ES6139DT MC100ES6139DTR2 MC100ES6139EJ MC100E

MC100ES6139 Applications

* The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal

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Clock Generation Chip Freescale Semiconductor
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