Overview: www.DataSheet4U.com Freescale Semiconductor Technical Data MC100ES6139 Rev 3, 06/2005 3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip
The MC100ES6139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a singleended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01 µF capacitor. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple ES6139s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one ES6139, the MR pin need not be exercised as the internal divider design ensures synchronization between the ÷2/4 and the ÷4/5/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100ES Series contains temperature compensation.
