MC100ES6039 - 3.3V ECL/PECL/HSTL/LVDS Generation Chip

Product Overview

Freescale Semiconductor

Part number	MC100ES6039
Manufacturer	Freescale Semiconductor
File Size	260.61 KB
Description	3.3V ECL/PECL/HSTL/LVDS Generation Chip
Datasheet	MC100ES6039 Datasheet
Additional preview pages of the MC100ES6039 datasheet.

ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff ÷2/4 Outputs ECL Diff ÷4/6 Outputs ECL Freq.

Select Input ÷2/4 ECL Freq.

Maximum Frequency >1.0 GHz Typical 50 ps Output-to-Output Skew PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE =.
3.135 V to.
3.8 V Open Input Default State Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips VBB Output LVDS and HSTL Input Compatible 20-Lead Pb-Free Package Available MC100ES603.

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Other Datasheets by Freescale Semiconductor

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Published: Feb 24, 2010 |