MC33780 Datasheet | Freescale Semiconductor

Features - Two Independent DBUS I/Os - mon SPI Interface for All Operations - Open-Drain Interrupt Output with Pull-up - Maskable Interrupts for Send and Receive Data Status - Automatic Message Cyclical Redundancy Checking (CRC) Generation and Checking - Four-Stage Transmit and Receive Buffers - 8- to 16-Bit Messages with 0- to 8-Bit CRC - Independent Frequency Spreading for Each Channel - Pb-Free Packaging Designated by Suffix Code EG DIFFERENTIAL DBUS MASTER EG (Pb-FREE SUFFIX) 98ASB42567B 16-TERMINAL SOICW ORDERING INFORMATION Device MC33780EG/R2 Temperature Range (TA) -40°C to 85°C Package 16 SOICW +5.0 V +25 V MCU VCC SCLK CS MOSI MISO RST INT CLK GND VCC 33780 VSUP Twisted Pair SCLK CS MOSI MISO RST INT CLK GND D0H D0L D1H D1L DSI/DBUS SLAVE 33793 DSI/DBUS SLAVE 33793 4.7 n F capacitors from D0H, D0L, D1H and D1L to circuit ground are required for proper operation. Figure 1. 33780 Simplified Application Diagram - This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. .. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VSUP CLK DSIF DSIS Protocol Engine DSIR DSIF DSIS DSIR SCLK MISO MOSI CS INT RST DBUS Driver/Receiver D0H D0L Spreader DBUS Driver/Receiver D1H D1L SPI, Registers and Interrupt Generator TLIM GND GND GND Figure 2. 33780 Internal Block...