MB90F342S
Overview
- Clock
- Built-in PLL clock frequency multiplication circuit
- Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
- Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided two) is allowed. (devices without Ssuffix only) *
