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  Fujitsu Electronic Components Datasheet  

MB91F610A Datasheet

32-bit Microcontrollers

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FUJITSU MICROELECTRONICS
DATA SHEET
32-bit Microcontrollers
CMOS
FR80 MB91610 Series
MB91F610A/613
DS07-16907-2E
DESCRIPTION
The MB91610 series is a line of Fujitsu Microelectronics microcontrollers based on a 32-bit RISC CPU core that
feature a variety of peripheral functions for embedded applications that demand high-performance and high-speed
CPU processing.
This series is based on the FR80* family CPU and is implemented as a single chip.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Microelectronics Limited.
FEATURES
FR80 CPU
• 32-bit RISC, load/store architecture, five-stage pipeline
• General-purpose registers : 32-bit × 16
• 16-bit fixed-length instructions (basic instructions) : 1 instruction per cycle
• Instructions suitable for embedded applications
- Memory-to-memory transfer, bit processing, barrel shift instructions, etc.
- Instruction support for high level languages
www.DataSheetF4Uu.ncocmtion entry and exit instructions, instructions for register multi-load and multi-store
- Bit search instruction
“1” detection, “0” detection, transition point detection
- Branch instructions with delay slots
Reduced overhead when processing branches
- Register interlock functions
Facilitate coding in assembly language
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2008-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.8


  Fujitsu Electronic Components Datasheet  

MB91F610A Datasheet

32-bit Microcontrollers

No Preview Available !

MB91610 Series
- Built-in multiplier/instruction-level support
- Signed 32-bit multiplication : 5 cycles
- Signed 16-bit multiplication : 3 cycles
- Interrupts (save PC and PS) : 6 cycles, 16 priority levels
- Harvard architecture allowing program access and data access to be executed simultaneously
- Instruction prefetch function has been added with 4 word instruction queue of CPU
• Instruction compatible with FR family CPU
- Additional bit search instructions
- No resource instructions and coprocessor instructions
• Maximum operating frequency
CPU : 33 MHz
Resources : 33 MHz
• DMA controller (DMAC)
8 channels
Address space : 32 bits (4 Gbytes)
Transfer modes : Block transfer/burst transfer/demand transfer
Address update : Increment/decrement/fixed (increment/decrement step size of 1, 2, or 4)
Transfer data length : Selectable from 8-bit, 16-bit, 32-bit
Block size : 1 to 16
Number of transfers : 1 to 65535
Transfer requests
- Requests from software
- Interrupt requests from peripheral resources (interrupt requests are shared, including external interrupts)
Reload functions : Reload can be specified on all channels
Priority order : Fixed (ch.0 > ch.1 > ch.2 > ch.3 > ...) or round-robin
Interrupt requests : Interrupts can be generated for transfer complete, transfer error, and transfer interrupted.
• Multifunction serial interface
www.DataSheet44Uc.choamnnels with 16-byte FIFO, 4 channels without FIFO
Operation mode is selectable from UART/CSIO/I2C for each channel (For ch.0, I2C is not available.)
UART
- Full-duplex double buffer
- Selectable parity on/off
- Built-in dedicated baud rate generator
- External clock can be used as a serial clock
- Error detection function for parity, frame and overrun errors
CSIO
- Full-duplex double buffer
- Built-in dedicated baud rate generator
- Overrun error detection function
I2C
- Supports both standard mode (Max 100 kbps) and Fast mode (Max 400 kbps)
- Some channels are 5 V tolerant
(Continued)
2 DS07-16907-2E


Part Number MB91F610A
Description 32-bit Microcontrollers
Maker Fujitsu Media Devices Limited
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