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GSI Technology

GS4288C09GL Datasheet Preview

GS4288C09GL Datasheet

288Mb CIO Low Latency DRAM

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GS4288C09/18/36L
144-Ball BGA
Commercial Temp
Industrial Temp
32M x 9, 16M x 18, 8M x 36
288Mb CIO Low Latency DRAM (LLDRAM) II
533 MHz300 MHz
2.5 V VEXT
1.8 V VDD
1.5 V or 1.8 V VDDQ
Features
• Pin- and function-compatible with Micron RLDRAM® II
• 533 MHz DDR operation (1.067Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency)
• 8M x 36, 16M x 18, and 32M x 9 organizations available
• 8 internal banks for concurrent operation and maximum
bandwidth
• Reduced cycle time (15 ns at 533 MHz)
• Address Multiplexing (Nonmultiplexed address option
available)
• SRAM-type interface
• Programmable Read Latency (RL), row cycle time, and burst
sequence length
• Balanced Read and Write Latencies in order to optimize data
bus utilization
• Data mask for Write commands
• Differential input clocks (CK, CK)
• Differential input data clocks (DKx, DKx)
• On-chip DLL generates CK edge-aligned data and output
data clock signals
• Data valid signal (QVLD)
• 32 ms refresh (8K refresh for each bank; 64K refresh
command must be issued in total each 32 ms)
• 144-ball BGA package
• HSTL I/O (1.5 V or 1.8 V nominal)
• 25–60matched impedance outputs
• 2.5 V VEXT, 1.8 V VDD, 1.5 V or 1.8 V VDDQ I/O
• On-die termination (ODT) RTT
• Commerical and Industrial Temperature
Commercial (+0° TC +95°C)
Industrial (–40° TC +95°C)
Introduction
The GSI Technology 288Mb Low Latency DRAM
(LLDRAM) II is a high speed memory device designed for
high address rate data processing typically found in networking
and telecommunications applications. The 8-bank architecture
and low tRC allows access rates formerly only found in
SRAMs.
The Double Data Rate (DDR) I/O interface provides high
bandwidth data transfers, clocking out two beats of data per
clock cycle at the I/O balls. Source-synchronous clocking can
be implemented on the host device with the provided free-
running data output clock.
Commands, addresses, and control signals are single data rate
signals clocked in by the True differential input clock
transition, while input data is clocked in on both crossings of
the input data clock(s).
Read and Write data transfers always in short bursts. The burst
length is programmable to 2, 4 or 8 by setting the Mode
Register.
The device is supplied with 2.5 V VEXT and 1.8 V VDD for the
core, and 1.5 V or 1.8 V for the HSTL output drivers.
Internally generated row addresses facilitate bank-scheduled
refresh.
The device is delivered in an efficent BGA 144-ball package.
Rev: 1.03 7/2014
1/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology




GSI Technology

GS4288C09GL Datasheet Preview

GS4288C09GL Datasheet

288Mb CIO Low Latency DRAM

No Preview Available !

32M x 9 Mb Ball Assignments—144-Ball BGA—Top View
GS4288C09/18/36L
1 2 3 4 5 6 7 8 9 10
A VREF VSS VEXT VSS
VSS VEXT
B VDD DNU3 DNU3 VSS
VSS DQ0
C VTT DNU3 DNU3 VDDQ
VDDQ
DQ1
D
A221 DNU3 DNU3
VSS
VSS QK0
E A211 DNU3 DNU3 VDDQ
VDDQ
DQ2
F
A5
DNU3 DNU3
VSS
VSS DQ3
G A8 A6 A7 VDD
VDD A2
H B2 A9 VSS VSS
VSS VSS
J NF2 NF2 VDD VDD
VDD VDD
K DK DK VDD VDD
VDD VDD
L REF CS VSS VSS
VSS VSS
M WE A16 A17 VDD
VDD A12
N A18 DNU3 DNU3 VSS
VSS DQ4
P A15 DNU3 DNU3 VDDQ
VDDQ
DQ5
R VSS DNU3 DNU3 VSS
VSS DQ6
T VTT DNU3 DNU3 VDDQ
VDDQ
DQ7
U VDD DNU3 DNU3 VSS
VSS DQ8
V VREF ZQ VEXT VSS
VSS VEXT
Notes:
1. Reserved for future use. This pin may be connected to ground.
2. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND.
3. Do not use. This pin may have parasitic characteristics of an I/O. It may be connected to GND.
11 12
TMS TCK
DNU3
DNU3
QK0
DNU3
VDD
VTT
VSS
A20
DNU3 QVLD
A1 A0
A4 A3
B0 CK
B1 CK
A14 A13
A11 A10
DNU3
DNU3
A19
DM
DNU3
DNU3
DNU3
VSS
VTT
VDD
TDO TDI
Rev: 1.03 7/2014
2/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology


Part Number GS4288C09GL
Description 288Mb CIO Low Latency DRAM
Maker GSI Technology
Total Page 30 Pages
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