GSI Technology GS81302S08E
The device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, C and C. Each Burst of 2 SigmaSIO DDR-II SRAM also supplies Echo Clock outputs, CQ and CQ, which are synchronized with read data output.| Part No. | GS81302S08E |
|---|---|
| Datasheet | GS81302S08E Download |
| Manufacturer |  GSI Technology |
| Description | 144Mb SigmaSIO DDR -II Burst of 2 SRAM |
| Buy | Stock & Price |
FEATURES
● Simultaneous Read and Write SigmaSIO™ Interface● JEDEC-standard pinout and package
● Dual Double Data Rate interface
● Byte Write controls sampled at data-in time
● DLL circuitry for wide output data valid window and future frequency scaling
● Burst of 2 Read and Write
● 1.8 V +100/–100 mV core power supply
● 1.5 V or 1.8 V HSTL Interface
● Pipelined read operation
● Fully coherent read and write pipelines
● ZQ mode pin for programmable output drive strength
● IEEE 1149.1 JTAG-compliant Boundary Scan
● 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
● RoHS-compliant 165-bump BGA package available SigmaSIO™ Family Overview GS81302S08/09/18/36 are built in compliance with the SigmaSIO DDR-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous device.
