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GS8161E36B - (GS8161E18B - GS8161E36B) Sync Burst SRAMs

Download the GS8161E36B datasheet PDF. This datasheet also covers the GS8161E18B variant, as both devices belong to the same (gs8161e18b - gs8161e36b) sync burst srams family and are provided as variant models within a single manufacturer datasheet.

General Description

Applications The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D) is a 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter.

Key Features

  • FT pin for user-configurable flow through or pipeline operation.
  • Dual Cycle Deselect (DCD) operation.
  • IEEE 1149.1 JTAG-compatible Boundary Scan.
  • 2.5 V or 3.3 V +10%/.
  • 10% core power supply.
  • 2.5 V or 3.3 V I/O supply www. DataSheet4U. com.
  • LBO pin for Linear or Interleaved Burst mode.
  • Internal input resistors on mode pins allow floating mode pins.
  • Default to Interleaved Pipeline mode.
  • Byte Write (BW) and/or Glo.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8161E18B_GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8161E36B
Manufacturer GSI Technology
File Size 1.99 MB
Description (GS8161E18B - GS8161E36B) Sync Burst SRAMs
Datasheet download datasheet GS8161E36B Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D) 100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply www.DataSheet4U.