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GS82582T37GE Datasheet Preview

GS82582T37GE Datasheet

288Mb SigmaDDR-II+ Burst of 2 SRAM

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GS82582T19/37GE-450/400/375/333
165-Bump BGA
Commercial Temp
Industrial Temp
288Mb SigmaDDR-II+TM
Burst of 2 SRAM
450 MHz–333 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
Features
• 2.0 Clock Latency
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• RoHS-compliant 165-bump BGA package
SigmaDDRFamily Overview
The GS82582T19/37GE are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 301,989,888-bit (288Mb)
SRAMs. The GS82582T19/37GE SigmaDDR-II+ SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS82582T19/37GE SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 18 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
-375
2.66 ns
0.45 ns
-333
3.0 ns
0.45 ns
Rev: 1.04 4/2016
1/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology




GSI Technology

GS82582T37GE Datasheet Preview

GS82582T37GE Datasheet

288Mb SigmaDDR-II+ Burst of 2 SRAM

No Preview Available !

GS82582T19/37GE-450/400/375/333
16M x 18 SigmaDDR-II+ SRAM—Top View
123456789
A CQ SA SA R/W BW1 K SA LD SA
B NC DQ9 NC SA SA K BW0 SA NC
C NC NC NC VSS SA NC SA VSS NC
D NC NC DQ10 VSS VSS VSS VSS VSS NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC DQ12 NC
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC DQ15 NC
VDDQ
VSS
VSS
VSS VDDQ NC
M NC NC NC VSS VSS VSS VSS VSS NC
N
NC
NC DQ16 VSS
SA
SA
SA
VSS NC
P NC NC DQ17 SA SA QVLD SA SA NC
R
TDO TCK
SA
SA
SA ODT SA
SA
SA
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Note:
BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17.
10
SA
NC
DQ7
NC
NC
NC
NC
VREF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
Rev: 1.04 4/2016
2/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology


Part Number GS82582T37GE
Description 288Mb SigmaDDR-II+ Burst of 2 SRAM
Maker GSI Technology
Total Page 27 Pages
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