Description
Applications The GS8321EV18/32/36E is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter.
Features
- FT pin for user-configurable flow through or pipeline operation.
- Dual Cycle Deselect (DCD) operation.
- IEEE 1149.1 JTAG-compatible Boundary Scan.
- 1.8 V +10%/.
- 10% core power supply.
- 1.8 V I/O supply.
- LBO pin for Linear or Interleaved Burst mode.
- Internal input resistors on mode pins allow floating mode pins.
- Default to Interleaved Pipeline mode.
- Byte Write (BW) and/or Global Write (GW) operation.
- Int.
GS8321EV18E Datasheet
