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GS8322Z72GC Datasheet Preview

GS8322Z72GC Datasheet

36Mb Pipelined and Flow Through Synchronous NBT SRAM

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GS8322Z72(C)
209 BGA
Commercial Temp
Industrial Temp
36Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 209-Bump BGA package
• RoHS-compliant package available
Functional Description
The GS8322Z72 is a 36Mbit Synchronous Static SRAM. GSI's
NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined
read/double late write or flow through read/single late write
SRAMs, allow utilization of all available bus bandwidth by
eliminating the need to insert deselect cycles when the device
is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8322Z72 may be configured by the user to operate in
Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising edge triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge-triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS8322Z72 is implemented with GSI's high performance
CMOS technology and is available in a JEDEC-standard 209-
bump BGA package.
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Parameter Synopsis
tKQ(x72)
tCycle
Curr (x72)
tKQ
tCycle
Curr (x72)
-250 -225 -200 -166 -150 -133 Unit
3.0 3.0 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
440 410 370 320 300 265 mA
6.5 7.0 7.5 8.0 8.5 8.5 ns
6.5 7.0 7.5 8.0 8.5 8.5 ns
315 295 265 255 240 230 mA
Rev: 1.08 10/2014
1/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology




GSI Technology

GS8322Z72GC Datasheet Preview

GS8322Z72GC Datasheet

36Mb Pipelined and Flow Through Synchronous NBT SRAM

No Preview Available !

GS8322Z72(C)
GS8322Z72C Pad Out—209-Bump BGA—Top View (Package C)
1 2 3 4 5 6 7 8 9 10 11
A DQG DQG A E2 A ADV A E3 A DQB DQB A
B
DQG DQG
BC
BG NC
W
A
BB BF DQB DQB B
C
DQG DQG
BH
BD
NC
E1
NC
BE
BA DQB DQB
C
D DQG DQG VSS NC NC G NC NC VSS DQB DQB D
E
DQPG DQPC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPF
DQPB
E
F DQC DQC VSS VSS VSS ZQ VSS VSS VSS DQF DQF F
G
DQC
DQC VDDQ VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQF
DQF
G
H DQC DQC VSS VSS VSS MCL VSS VSS VSS DQF DQF H
J
DQC
DQC VDDQ VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQF
DQF
J
K NC NC CK NC VSS CKE VSS NC NC NC NC K
L
DQH
DQH
VDDQ
VDDQ
VDD
FT
VDD
VDDQ
VDDQ
DQA
DQA
L
M DQH DQH VSS VSS VSS MCL VSS VSS VSS DQA DQA M
N
DQH
DQH VDDQ VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQA
DQA
N
P DQH DQH VSS VSS VSS ZZ VSS VSS VSS DQA DQA P
R
DQPD DQPH
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPA
DQPE
R
T
DQD DQD VSS
NC
NC LBO NC
NC VSS DQE DQE
T
U
DQD DQD
NC
A
NC
A
A
A
NC DQE DQE
U
V DQD DQD A A A A1 A A A DQE DQE V
W DQD DQD TMS TDI A A0 A TDO TCK DQE DQE W
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 1.08 10/2014
2/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology


Part Number GS8322Z72GC
Description 36Mb Pipelined and Flow Through Synchronous NBT SRAM
Maker GSI Technology
Total Page 29 Pages
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