GS8322Z18 Datasheet | GSI Technology

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) 119, 165 & 209 BGA mercial Temp Industrial Temp Features - NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-patible with both pipelined and flow through Nt RAM™, No BL™ and ZBT™ SRAMs - 2.5 V or 3.3 V +10%/- 10% core power supply - 2.5 V or 3.3 V I/O supply .. - User-configurable Pipeline and Flow Through mode - ZQ mode pin for user-selectable high/low output drive - IEEE 1149.1 JTAG-patible Boundary Scan - LBO pin for Linear or Interleave Burst mode - Pin-patible with 2Mb, 4Mb, 8Mb, and 16Mb devices - Byte write operation (9-bit Bytes) - 3 chip enable signals for easy depth expansion - ZZ Pin for automatic power-down - JEDEC-standard 119-, 165- or 209-Bump BGA package 36Mb Pipelined and Flow Through Synchronous NBT SRAM 250 MHz- 133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates plex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8322Z18/36/72 may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output...