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GS8662S18E-200 - DDR SigmaSIO-II SRAM

Download the GS8662S18E-200 datasheet PDF. This datasheet also covers the GS8662S08E-333 variant, as both devices belong to the same ddr sigmasio-ii sram family and are provided as variant models within a single manufacturer datasheet.

Description

Table Symbol SA NC R/W NW0 NW1 BW0 BW1 BW0 BW3 K C TMS TDI TCK TDO VREF ZQ K C DOFF LD CQ CQ Dn Qn VDD VDDQ VSS Description Synchronous Address Inputs No Connect Read/Write Contol Pin Synchronous Nybble Writes Synchronous Byte Writes Synchronous Byte Writes Input Clock Outpu

Features

  • Simultaneous Read and Write SigmaSIO™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • DLL circuitry for wide output data valid window and future frequency scaling.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully coherent read and write pipelines.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8662S08E-333_GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8662S18E-200
Manufacturer GSI Technology
File Size 2.29 MB
Description DDR SigmaSIO-II SRAM
Datasheet download datasheet GS8662S18E-200 Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS8662S18E-250 DDR SigmaSIO-II SRAM
GS8662S18E-167 DDR SigmaSIO-II SRAM
GS8662S18E-300 DDR SigmaSIO-II SRAM
GS8662S18E-333 DDR SigmaSIO-II SRAM
GS8662S18BD 72Mb SigmaSIO DDR -II Burst of 2 SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Preliminary GS8662S08/09/18/36E-333/300/250/200/167 www.DataSheet4U.com 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.