GS8662S18E-200
Features
- Simultaneous Read and Write Sigma SIO™ Interface
- JEDEC-standard pinout and package
- Dual Double Data Rate interface
- Byte Write controls sampled at data-in time
- DLL circuitry for wide output data valid window and future frequency scaling
- Burst of 2 Read and Write
- 1.8 V +100/- 100 m V core power supply
- 1.5 V or 1.8 V HSTL Interface
- Pipelined read operation
- Fully coherent read and write pipelines
- ZQ mode pin for programmable output drive strength
- IEEE 1149.1 JTAG-pliant Boundary Scan
- Pin-patible with future 144Mb devices
- 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
- Ro HS-pliant 165-bump BGA package available
72Mb Burst of 2 DDR Sigma SIO-II SRAM
333 MHz- 167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O
Bottom View
165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1
Sigma RAM™ Family Overview
GS8662S08/09/18/36 are built in pliance with the Sigma SIO-II SRAM pinout standard for Separate I/O synchronous SRAMs....
