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GSI Technology

GS8673EQ36BGK Datasheet Preview

GS8673EQ36BGK Datasheet

72Mb SigmaQuad-IIIe Burst of 2 ECCRAM

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GS8673EQ18/36BK-675/625/550/500
260-Ball BGA
Commercial Temp
Industrial Temp
72Mb SigmaQuad-IIIe™
Burst of 2 ECCRAM™
675 MHz–500 MHz
1.35V VDD
1.2V to 1.5V VDDQ
Features
• On-Chip ECC with virtually zero SER
• Configurable Read Latency (3.0 or 2.0 cycles)
• Simultaneous Read and Write SigmaQuad-IIIe™ Interface
• Separate I/O Bus
• Double Data Rate interface
• Burst of 2 Read and Write
• Pipelined read operation
• Fully coherent Read and Write pipelines
• 1.35V nominal VDD
• 1.2V JESD8-16A BIC-3 Compliant Interface
• 1.5V HSTL Interface
• ZQ pin for programmable output drive impedance
• ZT pin for programmable input termination impedance
• Configurable Input Termination
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package
–K: 5/6 RoHS-compliant package
–GK: 6/6 RoHS-compliant package
SigmaQuad-IIIeFamily Overview
SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS8673EQ18/36BK SigmaQuad-IIIe ECCRAMs are
synchronous devices. They employ dual, single-ended master
clocks, CK and CK. These clocks are single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. CK and CK are used to control the address and control
input registers, as well as all output timing.
The KD and KD clocks are dual mesochronous (with respect to
CK and CK) input clocks that are used to control the data input
registers. Consequently, data input setup and hold windows
can be optimized independently of address and control input
setup and hold windows.
Each internal read and write operation in a SigmaQuad-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 4M x 18 has
2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles, etc. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
Parameter Synopsis
Speed Bin
Operating Frequency
Data Rate (per pin)
-675 675 / 450 MHz 1350 / 900 Mbps
-625 625 / 400 MHz 1250 / 800 Mbps
-550 550 / 375 MHz
1100 / 750 Mbps
-500 500 / 333 MHz 1000 / 666 Mbps
Note: Please contact GSI for availability of 714 MHz devices.
Read Latency
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
VDD
1.3V to 1.4V
1.3V to 1.4V
1.25V to 1.4V
1.25V to 1.4V
Rev: 1.06 5/2012
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology




GSI Technology

GS8673EQ36BGK Datasheet Preview

GS8673EQ36BGK Datasheet

72Mb SigmaQuad-IIIe Burst of 2 ECCRAM

No Preview Available !

GS8673EQ18/36BK-675/625/550/500
4M x 18 (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13
A
VDD
VDDQ
VDD
VDDQ MCL
MCH
(CFG)
MCL
ZQ
PZT1 VDDQ VDD VDDQ VDD
B
VSS NUO VSS
NUI
MVQ
MCL
(B4M)
NC
(RSVD)
MCH
(SIOM)
PZT0
D0
VSS Q0
VSS
C Q17 VDDQ D17 VDDQ VSS SA VDD SA VSS VDDQ NUI VDDQ NUO
D
VSS NUO VSS
NUI
SA
VDDQ
NC
(288 Mb)
VDDQ
NC
(144 Mb)
D1
VSS Q1
VSS
E Q16 VDDQ D16 VDD VSS SA VSS SA VSS VDD NUI VDDQ NUO
F VSS NUO VSS NUI SA VDD VDDQ VDD SA D2 VSS Q2 VSS
G Q15 NUO D15 NUI VSS SA MZT1 SA VSS D3 NUI Q3 NUO
H Q14 VDDQ D14 VDDQ SA VDDQ W VDDQ SA VDDQ NUI VDDQ NUO
J VSS NUO VSS NUI VSS SA VSS SA VSS D4 VSS Q4 VSS
K CQ1 VDDQ VREF VDD KD1 VDD CK VDD KD0 VDD VREF VDDQ CQ0
L CQ1 VSS QVLD1 Vss KD1 VDDQ CK VDDQ KD0 VSS QVLD0 VSS CQ0
M VSS Q13 VSS D13 VSS SA VSS SA VSS NUI VSS NUO VSS
N NUO VDDQ NUI VDDQ DLL VDDQ R VDDQ MCH VDDQ D5 VDDQ Q5
P NUO Q12 NUI D12 VSS SA MZT0 SA VSS NUI D6 NUO Q6
R VSS Q11 VSS D11 MCH VDD VDDQ VDD RST NUI VSS NUO VSS
T NUO VDDQ NUI VDD VSS SA VSS SA VSS VDD D7 VDDQ Q7
U VSS Q10 VSS D10 NUI VDDQ ADZT1 VDDQ NUI NUI VSS NUO VSS
V
NUO VDDQ NUI VDDQ VSS
SA
(x18)
VDD
SA
(B2)
VSS VDDQ D8 VDDQ Q8
W
VSS
Q9
VSS
D9
TCK
RLM0
NC
(RSVD)
MCL
TMS
NUI
VSS
NUO
VSS
Y
VDD VDDQ VDD VDDQ TDO
ZT RLM1 MCL
TDI VDDQ VDD VDDQ VDD
Notes:
1. Pins 5A and 7A are reserved for future use. They must be tied Low in this device.
2. Pins 5R and 9N are reserved for future use. They must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied Low in this device to select Burst-of-2 configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
7. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
8. Pin 9D is reserved as address pin SA for 144 Mb devices. It is a true no connect in this device.
9. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
10. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low.
11. Pins 8W and 8Y are reserved for internal use only. They must be tied Low.
12. Pins 7B and 7W are reserved for future use. They are true no connects in this device.
Rev: 1.06 5/2012
2/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology


Part Number GS8673EQ36BGK
Description 72Mb SigmaQuad-IIIe Burst of 2 ECCRAM
Maker GSI Technology
Total Page 30 Pages
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