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GS881Z18T Datasheet Preview

GS881Z18T Datasheet

8Mb Pipelined and Flow Through Synchronous NBT SRAMs

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Preliminary
GS881Z18/36T-11/100/80/66
100-Pin TQFP 8Mb Pipelined and Flow Through 100 MHz–66 MHz
Commercial Temp
Industrial Temp
Synchronous NBT SRAMs
3.3 V VDD
2.5 V and 3.3 V VDDQ
Features
• 512K x 18 and 256K x 36 configurations
• User-configurable Pipelined and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
• Read-Write-Read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• Pin-compatible with 2M, 4M and 16M devices
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered, address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
Pipeline
3-1-1-1
Flow Through
2-1-1-1
-11 -100 -80
-66
tCycle 10 ns 10 ns 12.5 ns 15 ns
tKQ 4.5 ns 4.5 ns 4.8 ns 5 ns
IDD 210 mA 210 mA 190 mA 170 mA
tKQ 11 ns 12 ns 14 ns 18 ns
tCycle 15 ns 15 ns 15 ns 20 ns
IDD 150 mA 150 mA 130 mA 130 mA
Functional Description
The GS881Z18/36T is an 8Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising-edge-triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge-triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS881Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
BC
DE
F
Read/Write
R
WR
WR
W
Flow Through
Data I/O
Pipelined
Data I/O
QA DB QC DD QE
QA DB QC DD QE
Rev: 1.10 8/2000
1/34 © 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.




GSI Technology

GS881Z18T Datasheet Preview

GS881Z18T Datasheet

8Mb Pipelined and Flow Through Synchronous NBT SRAMs

No Preview Available !

GS881Z18T Pinout
Preliminary.
GS881Z18/36T-11/100/80/66
NC
NC
NC
VDDQ
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
FT
VDD
DP
VSS
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
512K x 18
72
71
11 Top View
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A18
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
QE
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
NC
VSS
VDDQ
NC
NC
NC
Rev: 1.10 8/2000
2/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1998, Giga Semiconductor, Inc.


Part Number GS881Z18T
Description 8Mb Pipelined and Flow Through Synchronous NBT SRAMs
Maker GSI Technology
Total Page 30 Pages
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