ddr i/ii termination regulator.
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General Description
The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 (Se.
of the chipset and DIMMs. The G2996 can easily provide the accurate VTT and VREF voltages without external resistors tha.
The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 (Series Stub Termination Logic) specifications for termination of DDR-SDRAM. It contains a high-speed operational amplifier that provides excellent response to the .
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