* High speed operation tpd (CLK or CLK to Q) = 35 ns (typ)
* High output current Fanout of 10 LS TTL Loads
* Wide operating voltage Vcc = 2 to 6 V
* Low s.

Down count at the rise edge of clock (CLK), Down count at the fall edge of clock ( CLK ) Jn data is preset at the rise of clock (CLK), the fall of clock (CLK ) Clock inputs (CLK, CLK ) is CMOS level Clock inputs (CLK, CLK ) is TTL level Initialize of.

HD151012

HD151015

HD151005

HD151BF854

HD151TS301RP

HD151TS302ARP

HD151TS302RP

HD151TS304ARP

HD151TS305RP

HD1520FX

HD153009

HD153011

HD153013