HD74HC165 Datasheet | Hitachi Semiconductor

Parallel-load 8-bit Shift Register Description This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a plementary output from the eighth bit. Clocking is acplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the register independent of the state of the clock. Features - - - - - High Speed Operation: tpd (Clock to QH) = 21 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs Parallel Shift/Load L H H H H Clock Inhibit X L L L H X Clock X L Serial X X H L X A - - - - - - H a - - - - - - h X X X X Internal outputs QA a QA0 H L QA0 QB b QB0 QAn QAn QB0 Output QH h QH0 QGn QGn QH0 Pin Arrangement Shift/ Load 1 CK E F G H QH D C B A QH 16 VCC Clock 15 Inhibit 14 D 13 C 12 B 11 A 10 Serial-In 9 QH (Top view) Parallel Inputs Clock 2 E 3 F 4 Parallel Inputs G 5 H 6 QH 7 GND 8 Timing Diagram Clock Clock Inhibit Serial Input Shift/Load A B C D Data E F G H Output QH Output QH Inhibit Load H L H L H L H H H L H L L H H L L H H L L H H L Serial Shift DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to +85°C Max - - - 0.5 1.35 1.8 - - - -...