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HD74HC390 - Dual Decade Counters

Description

The HD74HC390 incorporate dual decade counters, each composed of a divide-by-two and a divide-byfive counter.

The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual biquinary, or various combinations up to a single divide-by-100 counter.

Features

  • High Speed Operation: tpd (Clock A to QA) = 11 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Clock A X B X X X Clear H L L Operation Clear ÷2 and ÷5 Increment ÷2 Increment ÷5 HD74HC390 Pin Arrangement 1A 1Clear 1QA Output 1B 1QB Outputs 1QC 1QD GND 1 2 3 4 5 6 7 8 (Top view) CL.

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📁 Similar Datasheet

Part Number Description Manufacturer
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Part Number Description
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HD74HC390 Dual Decade Counters Description The HD74HC390 incorporate dual decade counters, each composed of a divide-by-two and a divide-byfive counter. The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual biquinary, or various combinations up to a single divide-by-100 counter. The HD74HC390 is incremented on the high to low transition (negative edge) of the clock input, and each has an independent clear input. When clear is set high all four bits of each counter are set to a low level. This enables count truncation and allows the implementation of divide-by-N counter configurations.
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