HD74HCT240 outputs) equivalent, octal buffers/line drivers/line receivers(with inverted 3-state outputs).
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* LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A to Y) = 11 ns typ (CL = 50 pF.
The HD74HCT240 is an inverting buffer and has two active low enables (1 G and 2G ). Each enable independently controls 4 buffers. This device does not have schmitt trigger inputs.
Features
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* LSTTL Output Logic Level.
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