H55S2532JFR-75M - 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O

This page provides the datasheet information for the H55S2532JFR-75M, a member of the H55S2622JFR-60M 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O family.

Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).

SK Hynix

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H55S2532JFR-75M 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O by Hynix Semiconductor - Datasheet Preview — Datasheet preview – H55S2532JFR-75M

Datasheet Details

Part number	H55S2532JFR-75M
Manufacturer	SK Hynix
File Size	1.25 MB
Description	256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O
Datasheet	H55S2532JFR-75M Datasheet
Additional preview pages of the H55S2532JFR-75M datasheet.

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Other Datasheets by Hynix Semiconductor

H55S2532JFR-60M - 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O
H55S2532JFR-A3M - 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O
H55S2562JFR-60M - 256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O
H55S2562JFR-75M - 256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O
H55S2562JFR-A3M - 256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O
H55S2622JFR-60M - 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O
H55S2622JFR-75M - 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O
H55S2622JFR-A3M - 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O

Full PDF Text Transcription

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www.DataSheet4U.com 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O Specification of 256M (8Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Nov. 2008 1 11256Mbit (8Mx32bit) Mobile SDR www.DataSheet4U.com H55S2622JFR Series H55S2532JFR Series Document Title 4Bank x 2M x 32bits Synchronous DRAM Revision History Revision No. 0.1 0.2 1.0 Initial Draft IDD Specification updated The final version History Draft Date May 2008 May 2008 Nov. 2008 Remark Preliminary Preliminary Rev 1.0 / Nov. 2008 2 11256Mbit (8Mx32bit) Mobile SDR www.DataSheet4U.

Published: May 3, 2010 |