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HY57V561620CT - 4 Banks x 4M x 16Bit Synchronous DRAM

General Description

The HY57V561620C(L)T(P) Series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

HY57V561620C(L)T(P) Series is organized as 4banks of 4,194,304x16.

Key Features

  • Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch (Leaded Package or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM Internal four banks operation.
  • Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full pa.

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Datasheet Details

Part number HY57V561620CT
Manufacturer SK Hynix
File Size 251.31 KB
Description 4 Banks x 4M x 16Bit Synchronous DRAM
Datasheet download datasheet HY57V561620CT Datasheet

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www.DataSheet4U.com HY57V561620C(L)T(P) 4 Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The HY57V561620C(L)T(P) Series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620C(L)T(P) Series is organized as 4banks of 4,194,304x16. HY57V561620C(L)T(P) Series is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.