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HY5S5B2BLF-6E - 256M (8Mx32bit) Mobile SDRAM

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General Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Overview

256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O Specification of 256M (8Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x32 This document is a general.

Key Features

  • Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).

More Datasheets from SK Hynix

Part Number Description
HY5S5B2BLF-HE 256M (8Mx32bit) Mobile SDRAM
HY5S5B2BLF-SE 256M (8Mx32bit) Mobile SDRAM
HY5S5B2BLFP-6E 256M (8Mx32bit) Mobile SDRAM
HY5S5B2BLFP-HE 256M (8Mx32bit) Mobile SDRAM
HY5S5B2BLFP-SE 256M (8Mx32bit) Mobile SDRAM
HY5S5B2CLFP-6E 256M (8Mx32bit) Mobile SDRAM
HY5S5B2CLFP-HE 256M (8Mx32bit) Mobile SDRAM
HY5S5B2CLFP-SE 256M (8Mx32bit) Mobile SDRAM
HY5S5B6ELF-HE 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
HY5S5B6ELF-SE 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O