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HY5S5B2CLFP-6E - 256M (8Mx32bit) Mobile SDRAM

General Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

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Overview

256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O Specification of 256M (8Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x32 This document is a general.

Key Features

  • Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).