Datasheet4U Logo Datasheet4U.com

HY5S6B6x - (HY5S6B6D/L/S/F/P) 4Banks x 1M x 16-Bits SDRAM

This page provides the datasheet information for the HY5S6B6x, a member of the HY5S6B6D (HY5S6B6D/L/S/F/P) 4Banks x 1M x 16-Bits SDRAM family.

Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • Standard SDRAM Protocol Internal 4bank operation.
  • Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage interface to reduce I/O power Low Power Features - PASR(Partial Array Self Refresh) - AUTO TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) - Deep Power Down Mode Programmable CAS latency of 1, 2 or 3 Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead) HY5S6B6D(L/S)FP : Lead Free HY5S6B6D(L/S)F : Lead.

📥 Download Datasheet

Datasheet preview – HY5S6B6x

Datasheet Details

Part number HY5S6B6x
Manufacturer SK Hynix
File Size 386.10 KB
Description (HY5S6B6D/L/S/F/P) 4Banks x 1M x 16-Bits SDRAM
Datasheet download datasheet HY5S6B6x Datasheet
Additional preview pages of the HY5S6B6x datasheet.

📁 Similar Datasheet

  • HY5-P - Current Transducers HY 5 to 25-P (LEM)
  • HY50-P - Current Transducer HY 50-P (LEM)
  • HY5002 - 1-chip composed of high-current totem pole (HAWYANG)
  • HY5012A - N-Channel Enhancement Mode MOSFET (HOOYI)
  • HY5012W - N-Channel Enhancement Mode MOSFET (HOOYI)
  • HY50P - Current Transducers/ HY 50-P/SP1 (LEM)
  • HY5100 - 2 Input / 3 Output Digital Delay Line (Hytek)
  • HY510N - PC POWER SUPPLY SUPERVISOR (HawYang)
  • HY5110A - N-Channel Enhancement Mode MOSFET (HUAYI)
  • HY5110NA2W - N-Channel Enhancement Mode MOSFET (HUAYI)
Other Datasheets by Hynix Semiconductor

Full PDF Text Transcription

Click to expand full text
Document Title 4Bank x 1M x 16bits Synchronous DRAM Revision History w w w Revision No. 0.1 0.2 0.3 Initial Draft .D at h S a t e e 4U . m o c HY5S6B6D(L/S)F(P)-xE 4Banks x1M x 16bits Synchronous DRAM History Draft Date Sep. 2003 Oct. 2003 Nov. 2003 July 2004 Remark Preliminary Preliminary Append Super-Low Power Group to the Data-sheet Changed DC Characteristics Changed Package Information w w w .D t a S a e h t e U 4 .c m o This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.3 / July 2004 1 w w w .D at h S a t e e 4U .
Published: |