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SK Hynix Electronic Components Datasheet

HYMP112S64LMP8 Datasheet

DDR2 SDRAM SO-DIMM

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Revision History
No. History
0.1
1) Defined target spec.
2) Corrected Pin assignment table
128Mx64 bits
DDR2 SDRAM SO-DIMM
HYMP112S64(L)MP8
Date
July 2004
Remark
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/ July 2004
1


SK Hynix Electronic Components Datasheet

HYMP112S64LMP8 Datasheet

DDR2 SDRAM SO-DIMM

No Preview Available !

www.DataSheet4U.com
DESCRIPTION
128Mx64 bits
DDR2 SDRAM SO-DIMM
HYMP112S64(L)MP8
Hynix HYMP112S64MP8 series is unbuffered 200-pin double data rate 2 Synchronous DRAM Small Outline Dual In-Line Memory Mod-
ules (DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMP112S64MP8 series consists of eight 128Mx8
DDR2 SDRAMs in 63 ball FBGA Dual Die Pacakge(DDP)s. Hynix HYMP112S64MP8 series provide a high performance 8-byte interface
in 67.60mm X 30.00mm form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMP512S64MP8 series is designed for high speed and offers fully synchronous operations referenced to both rising and falling
edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data
strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4-
bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_1.8. High speed frequen-
cies, programmable latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMP512S64MP8 series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial
2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the
information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 1GB (128M x 64) Unbuffered DDR2 SO - DIMM based on
128Mx8 DDR2 DDP SDRAMs
• JEDEC standard Double Data Rate2 Synchronous DRAMs
(DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply
• All inputs and outputs are compatible with SSTL_1.8 inter-
face
• OCD (Off-Chip Driver Impedance Adjustment) and ODT
(On-Die Termination)
• Fully differential clock operations (CK & /CK)
• Programmable CAS Latency 3 / 4 /5 supported
• Programmable Burst Length 4 / 8 with both sequential and
interleave mode
• Auto refresh and self refresh supported
7.8us refresh period at Lower than TCASE 85, 3.9us( 85
℃ < TCASE ≤ 95℃)
• Serial Presence Detect(SPD) with EEPROM
• Lead free product
ORDERING INFORMATION
Type
Part No.
PC2-3200 (DDR2-400)
PC2-4300 (DDR2-533)
HYMP112S64(L)MP8-E4
HYMP112S64(L)MP8-E3
HYMP112S64(L)MP8-C5
HYMP112S64(L)MP8-C4
Description
2 rank 1GB
Lead-free SO-DIMM
CL-tRCD-tRP
4-4-4
3-3-3
5-5-5
4-4-4
Form Factor
200pin Unbuffered SO-
DIMM
67.60 mm x 30,00 mm
(MO-224)
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/ July 2004
2


Part Number HYMP112S64LMP8
Description DDR2 SDRAM SO-DIMM
Maker Hynix Semiconductor
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