ICS43002I-41 attenuator equivalent, femtoclocks-tm vcxo based sonet/sdh jitter attenuator.
* (2) Differential LVPECL outputs
* Selectable CLKx, nCLKx differential input pairs
* CLKx, nCLKx pairs can accept the following differential input levels: LV.
where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are casca.
The ICS843002I-41 is a member of the HiperClockS™ family of high performance clock HiPerClockS™ solutions from ICS. The ICS843002I-41 is a PLL based synchronous clock generator that is optimized for SONET/SDH line card applications where jitter atten.
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