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ICS487-25 Datasheet Preview

ICS487-25 Datasheet

Quad PLL

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ICS487-25 pdf
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ICS487-25
Quad PLL for DTV
Description
The ICS487-25 generates five high-quality,
high-frequency clock outputs. It is designed to replace
crystals and crystal oscillators in DTV applications.
Using ICS’ patented Phase Locked Loop (PLL)
techniques, the device runs from a lower frequency
crystal or clock input.
Because there is zero ppm frequency synthesis error
on the audio clocks, the audio will remain locked to the
video.
Features
Packaged in 16-pin TSSOP
Available in Pb-free packaging
Replaces multiple crystals and oscillators
Input crystal or clock frequency of 27 MHz
Zero ppm frequency synthesis error
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low power CMOS process
Block Diagram
2
S1:0
27 MHz
clock or
crystal
input
X1/ICLK
X2
Crystal
Oscillator/
Clock
Buffer
External capacitors
may be required.
VDD
3
PLL1
PLL2
PLL3
ACLK
20M
48M
33.0M
PLL4
24.576M
3
GND
PDTS (all outputs and PLLs)
MDS 487-25 A
1
Revision 050604
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com



ICS
ICS

ICS487-25 Datasheet Preview

ICS487-25 Datasheet

Quad PLL

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ICS487-25 pdf
Pin Assignment
X1/ICLK
S0
S1
48M
VDD
GND
20M
24.576M
1
2
3
4
5
6
7
8
16 X2
15 VDD
14 PDTS
13 GND
12 VDD
11 GND
10 33.0M
9 ACLK
16 pin (173 mil) TSSOP
ICS487-25
Quad PLL for DTV
ACLK Output Selection Table
S1 S0
00
01
10
11
ACLK (MHz)
18.432
16.9344
12.288
18.432
Note: When S1 and S0 are switched, all other output
clocks will remain stable throughout the transition.
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
X1/ICLK
S0
S1
48M
VDD
GND
20M
24.576M
ACLK
33.0M
GND
VDD
GND
PDTS
VDD
X2
Pin
Type
Pin Description
Input Crystal connection. Connect to 27 MHz crystal or clock input.
Input Select pin 0. Determines ACLK output frequency per table above.
Internal pull up resistor.
Input Select pin 1. Determines ACLK output frequency per table above.
Internal pull up resistor.
Output 48 MHz clcok output. Weak internal pull-down when tri-state.
Power Connect to +3.3 V.
Power Connect to ground.
Output 20 MHz clock output. Weak internal pull-down when tri-state.
Output 24.576 MHz clock output. Weak internal pull-down when tri-state.
Output Audio clock output. Determined by table above. Weak internal
pull-down when tri-state
Output 33.0 MHz clock output. Weak internal pull-down when tri-state.
Power Connect to ground.
Power Connect to +3.3 V.
Power Connect to ground.
Input
Powers down entire chip and tri-states outputs when low. Internal
pull-up resistor.
Power Connect to +3.3 V.
Input Connect to 27 MHz crystal or float for clock input.
MDS 487-25 A
2
Revision 050604
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com


Part Number ICS487-25
Description Quad PLL
Maker ICS
Total Page 6 Pages
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