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ICS487-25 - QUAD PLL

General Description

The ICS487-25 generates five high-quality, high-frequency clock outputs.

It is designed to replace crystals and crystal oscillators in DTV applications.

Using IDT’s patented Phase Locked Loop (PLL) techniques, the device runs from a lower frequency crystal or clock input.

Key Features

  • Packaged in 16-pin TSSOP (Pb-free).
  • Replaces multiple crystals and oscillators.
  • Input crystal or clock frequency of 27 MHz.
  • Zero ppm frequency synthesis error.
  • Duty cycle of 45/55.
  • Operating voltage of 3.3 V.
  • Advanced, low power CMOS process Block Diagram 2 S1:0 27 MHz clock or crystal input X1/ICLK X2 Crystal Oscillator/ Clock Buffer External capacitors may be required. VDD 3 PLL1 PLL2 PLL3 ACLK 20M 48M 33.0M PLL4 24.576M.

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QUAD PLL FOR DTV DATASHEET ICS487-25 Description The ICS487-25 generates five high-quality, high-frequency clock outputs. It is designed to replace crystals and crystal oscillators in DTV applications. Using IDT’s patented Phase Locked Loop (PLL) techniques, the device runs from a lower frequency crystal or clock input. Because there is zero ppm frequency synthesis error on the audio clocks, the audio will remain locked to the video. Features • Packaged in 16-pin TSSOP (Pb-free) • Replaces multiple crystals and oscillators • Input crystal or clock frequency of 27 MHz • Zero ppm frequency synthesis error • Duty cycle of 45/55 • Operating voltage of 3.