ICS ICS487-25
The ICS487-25 generates five high-quality, high-frequency clock outputs. It is designed to replace crystals and crystal oscillators in DTV applications. c o m ICS487-25 Quad PLL for DTV External Components Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS487-25 must be isolated from system power supply noise to perform optimally.| Part No. | ICS487-25 |
|---|---|
| Datasheet | ICS487-25 Download |
| Manufacturer |  ICS |
| Description | Quad PLL |
| Buy | Stock & Price |
FEATURES
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● Packaged in 16-pin TSSOP Available in Pb-free packaging Replaces multiple crystals and oscillators Input crystal or clock frequency of 27 MHz Zero ppm frequency synthesis error Duty cycle of 45/55 Operating voltage of 3.3 V Advanced, low power CMOS process
DESCRIPTION
Using ICS’ patented Phase Locked Loop (PLL) techniques, the device runs from a lower frequency crystal or clock input. Because there is zero ppm frequency synthesis error on the audio clocks, the audio will remain locked to the video. Block Diagram VDD 3 2 S1:0 PLL1 ACLK 20M PLL2 48M PLL3 33.0M 27 MHz clock or crystal input X1/ICLK X2 Crystal Oscillator/ Clock Buffer PLL4 24.576M External capacitors may be required. 3 GND PDTS (all outputs and PLLs) MDS 487-25 A I nt eg ra te d Cir c uit S ys t em s l 1 52 5 Race Stree t, Sa n Jose, CA 95 126 l Revision 050604 tel (4 08) 297-1 201 l w ww. i c s t . c o m ICS487-25 Quad PLL for DTV Pin Assignment X1/ICLK S0 S1 48M VDD GND 20M 24.576M 1 2 3 4 5 6 7...
