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ICS844004I-04 Datasheet Preview

ICS844004I-04 Datasheet

CRYSTAL/LVCMOS-TO-LVDS FREQUENCY SYNTHESIZER

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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS844004I-04 is a 4 output LVDS
ICS Synthesizer optimized to generate clock
HiPerClockS™ frequencies for a variety of high performance
applications and is a member of the
HiPerClocksTM family of high performance
clock solutions from ICS. This device can select its input
reference clock from either a crystal input or a single-
ended clock signal. It can be configured to generate 4
outputs with individually selectable divide-by-one or
divide-by-four function via the 4 frequency select pins
(F_SEL[3:0]). The ICS844004I-04 uses ICS’ 3rd generation
low phase noise VCO technology and can achieve 1ps
or lower typical rms phase jitter. This ensures that it
will easily meet clocking requirements for SDH (STM-1/
STM-4/STM-16) and SONET (OC-3/OC12/OC-48). This
device is suitable for multi-rate and multiple port line
card applications. The ICS844004I-04 is conveniently
packaged in a small 24-pin TSSOP package.
FEATURES
• Four LVDS outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following applications: SONET/SDH, SATA,
or 10Gb Ethernet
• Output frequency range: 140MHz - 170MHz,
560MHz - 680MHz
• VCO range: 560MHz - 680MHz
• Crystal oscillator and CLK range: 17.5MHz - 21.25MHz
• RMS phase jitter @ 622.08MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.71ps (typical)
• RMS phase jitter @ 156.25MHz output, using a 19.53125MHz
crystal (1.875MHz - 20MHz): 0.51ps (typical)
• RMS phase jitter @ 155.52MHz output, using a 19.44MHz
crystal (12kHz - 5MHz): 0.75ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL_IN
OSC
XTAL_OUT
CLK Pulldown
INPUT_SEL Pulldown
0
1
MR Pulldown
F_SEL0 Pullup
F_SEL1 Pullup
Phase
Detector
VCO
M = ÷32
÷1
÷4
F_SEL2 Pullup
0 Q0
nQ0
1
0 Q1
1 nQ1
0 Q2
1 nQ2
nQ1
Q1
VDDo
Q0
nQ0
MR
F_SEL3
nc
VDDA
F_SEL0
VDD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24 nQ2
23 Q2
2 2 VDDO
21 Q3
20 nQ3
19 GND
18 F_SEL2
17 INPUT_SEL
16 CLK
15 GND
14 XTAL_IN
13 XTAL_OUT
ICS844004I-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
0 Q3
1 nQ3
F_SEL3 Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844004AGI-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
1




ICS

ICS844004I-04 Datasheet Preview

ICS844004I-04 Datasheet

CRYSTAL/LVCMOS-TO-LVDS FREQUENCY SYNTHESIZER

No Preview Available !

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1, 2 nQ1, Q1 Output
Differential output pair. LVDS interface levels.
3, 22
4, 5
6
7,
10,
12,
18
VDDO
Q0, nQ0
MR
F_SEL3,
F_SEL0,
F_SEL1,
F_SEL2
Power
Ouput
Input
Output supply pins.
Differential output pair. LVDS interface levels.
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Input Pullup Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3.
8 nc Unused
No connect.
9
11
13, 14
V
DDA
VDD
XTAL_OUT,
XTAL_IN
Power
Power
Input
Analog supply pin.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
15, 19
GND
Power
Power supply ground.
16
CLK
Input Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or CLK inputs as the the PLL Reference source.
17 INPUT_SEL Input Pulldown Selects XTAL inputs when LOW. Selects CLK when HIGH.
LVCMOS/LVTTL interface levels.
20, 21 nQ3, Q3 Output
Differential output pair. LVDS interface levels.
23, 24 Q2, nQ2 Output
Differential output pair. LVDS interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
R
PULLDOWN
RPULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3. OUTPUT CONFIGURATION AND FREQUENCY RANGE FUNCTION TABLE
Inputs
F_SELx XTAL (MHz)
0 19.44
1 19.44
0 18.75
VCO
(MHz)
622.08
622.08
600
N Divider Value
N0:N3
1
4
1
Output Frequency (MHz)
Q0/nQ0:Q3/nQ3
622.08
155.52
600
1
18.75
600
4
150
0
19.53125
625
1
625
1
19.53125
625
4
156.25
0 20.141601 644.5312
1
644.5312
1 20.141601 644.5312
4
161.13
Application
SONET/SDH
SATA
10 Gigabit Ethernet
10 Gigabit Ethernet
66B/64B FEC
844004AGI-04
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 26, 2006


Part Number ICS844004I-04
Description CRYSTAL/LVCMOS-TO-LVDS FREQUENCY SYNTHESIZER
Maker ICS
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