differential-to-lvpecl buffer/divider.
* 2 LVPECL outputs
* Frequency divide select options: ÷ 1, ÷ 2, ÷4, ÷8, ÷16
* IN, nIN input can accept the following differential input levels: LVPECL, LVDS, .
Termination input. Non-inver ting LVPECL differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 15, 1.
The ICS889874 is a high speed 1:2 Differentialto-LVPECL Buffer/Divider and is a member of HiPerClockS™ the HiPerClockS ™ family of high performance clock solutions from ICS. The ICS889874 has a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output divider, which all.
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