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ICS889874 Datasheet

DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER

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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS889874
1:2
DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
GENERAL DESCRIPTION
ICS
The ICS889874 is a high speed 1:2 Differential-
to-LVPECL Buffer/Divider and is a member of
HiPerClockS™ the HiPerClockS family of high performance
clock solutions from ICS. The ICS889874 has
a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output divider,
which allows the device to be used as either a 1:2 fanout
buffer or frequency divider. The clock input has internal
termination resistors, allowing it to interface with several
differential signal types while minimizing the number of
required external components. The device is packaged in
a small, 3mm x 3mm VFQFN package, making it ideal for
use on space-constrained boards.
FEATURES
2 LVPECL outputs
Frequency divide select options: ÷ 1, ÷ 2, ÷4, ÷8, ÷16
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
Output frequency: > 2.5GHz
Output skew: 5ps (typical)
Part-to-part skew: TBD
Additive jitter, RMS: <0.03ps (design target)
Supply voltage range: (LVPECL), 2.375V to 3.465V
Supply voltage range: (ECL), -3.465V to -2.375V
-40°C to 85°C ambient operating temperature
Pin compatible with SY89874U
BLOCK DIAGRAM
S2
nRESET
IN
VT
nIN
S0
S1
Enable
FF
Enable
MUX
Decoder
00 ÷2
01 ÷4
10 ÷8
11 ÷16
0
1
PIN ASSIGNMENT
Q0
nQ0
16 15 14 13
Q0 1
12 IN
nQ0 2
11 VT
Q1 3
1 0 VREF_AC
nQ1 4
9 nIN
5678
Q1
nQ1 ICS889874
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
VREF_AC
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
889874AK
www.icst.com/products/hiperclocks.html
REV. A MAY 19, 2004
1




ICS

ICS889874 Datasheet Preview

ICS889874 Datasheet

DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER

No Preview Available !

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS889874
1:2
DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2 Q0, nQ0 Output
Differential output pair. LVPECL / ECL interface levels.
3, 4 Q1, nQ1 Output
Differential output pair. LVPECL / ECL interface levels.
5, 15, 16 S2, S1, S0 Input Pullup Select pins. LVCMOS/LVTTL interface levels.
6 nc Unused
No connect.
7, 14
8
VCC
nRESET
Power
Input
Pullup
Positive supply pins.
Synchronizing enable/disable pin. When LOW, resets the divider. When
HIGH, unconnected. Input threshold is VCC/2V. Includes a 37kpull-up
resistor. LVTTL / LVCMOS interface levels.
9 nIN Input
Inverting differential LVPECL clock input.
10
VREF_AC
Output
11 VT Input
12 IN Input
Reference voltage for AC-coupled applications.
Termination input.
Non-inverting LVPECL differential clock input.
13 VEE Power
Negative supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
RPULLUP Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum Units
K
889874AK
www.icst.com/products/hiperclocks.html
2
REV. A MAY 19, 2004


Part Number ICS889874
Description DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
Maker ICS
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