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ICS548-03 Datasheet Preview

ICS548-03 Datasheet

Low Skew Clock Inverter and Divider

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ADVANCE INFORMATION
ICS548-03
Low Skew Clock Inverter and Divider
Description
Features
The ICS548-03 is a low cost, low skew, high
performance general-purpose clock designed to
produce a set of one output clock, one inverted
output clock, and one clock divided-by-2. Using
our patented analog Phase-Locked Loop (PLL)
techniques, the device operates from a frequency
range from 10 MHz to 120 MHz in the PLL mode,
and up to 160 MHz in the non-PLL mode.
In applications that to need maintain low phase
noise in the clock tree, the non-PLL (when
S3=S2=1) mode should be used.
• Packaged in 16 pin narrow (150 mil) SOIC
• Input clock up to 160 MHz in the non-PLL mode
• Provides clock outputs of CLK, CLK, and CLK/2
• Low skew (500 ps) on CLK, CLK, and CLK/2
• All outputs can be tri-stated
• Entire chip can be powered down by changing one
or two select pins
• 3.3V or 5.0V operating voltage
This chip is not a zero delay buffer. Many
applications may be able to use the ICS527 for zero
delay dividers.
Block Diagram
S3:S0
Clock Input
4
Input
Buffer
Clock
Synthesis
and
Divider
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
CLK
CLK
CLK/2
OE (All outputs)
MDS 548-03
1 Revision 042700
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com




ICST

ICS548-03 Datasheet Preview

ICS548-03 Datasheet

Low Skew Clock Inverter and Divider

No Preview Available !

ADVANCE INFORMATION
ICS548-03
Low Skew Clock Inverter and Divider
Pin Assignment
ICLK
VDD
VDD
S3
GND
GND
S2
S0
1
2
3
4
5
6
7
8
16 DC
15 DC
14 DC
13 CLK
12 CLK
11 CLK/2
10 OE
9 S1
CLK, CLK, and CLK/2 Select Table (in MHz)
S3 S2 S1 S0 CLK, CLK CLK/2
0000
Low
Low
0 0 0 1 Input/4 Input/8
0 0 1 0 Input Input/2
0 0 1 1 Input/2 Input/4
0100
Low
Low
0 1 0 1 Input x 2 Input
0 1 1 0 Input/5 Input/10
0 1 1 1 Input/3 Input/6
1000
Low
Low
1 0 0 1 Input/4 Input/8
1 0 1 0 Input Input/2
1 0 1 1 Input/2 Input/4
1100
Low
Low
1 1 0 1 Input/6 Input/12
1 1 1 0 Input/8 Input/16
1 1 1 1 Input/2 Input/4
PLL Input Range
Off Power down
On 20 -120
On 20 -120
On 20 -120
Off Power down
On 20 - 60
On 20 -120
On 20 - 120
Off Power down
On 10 - 60
On 10 - 60
On 10 - 60
Off Power down
Off 0 - 160
Off 0 - 160
Off 0 - 160
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
ICLK
VDD
VDD
S3
GND
GND
S2
S0
S1
OE
CLK/2
CLK
CLK
DC
DC
DC
Type
CI
P
P
I
P
P
I
I
I
I
O
O
O
-
-
-
Description
Input Clock. Connect to a CMOS level input clock.
Connect to +3.3V or +5.0V.
Connect to +3.3V or +5.0V.
Clock Select Pin 3. See above table.
Connect to ground.
Connect to ground.
Clock Select Pin 2. See above table.
Clock Select Pin 0. See above table.
Clock Select Pin 1. See above table.
Output Enable. Tri-states all clock outputs when low.
Clock Output divided by 2. See above table.
Clock Output. See above table.
Inverted Clock Output. See above table.
Don't Connect. Do not connect anything to this pin.
Don't Connect. Do not connect anything to this pin.
Don't Connect. Do not connect anything to this pin.
Key: I = Input; O = Output; P = Power Supply connection; CI = Clock Input
MDS 548-03
2 Revision 042700
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com


Part Number ICS548-03
Description Low Skew Clock Inverter and Divider
Maker ICST
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ICS548-03 Datasheet PDF





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