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MK2308-2 Datasheet Preview

MK2308-2 Datasheet

ZERO DELAY LOW SKEW BUFFER

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MK2308-2
ZERO DELAY, LOW SKEW BUFFER
Description
The MK2308-2 is a low jitter, low skew, high
performance Phase-Lock Loop (PLL) based zero delay
buffer for high speed applications. Based on ICS’
proprietary low jitter PLL techniques, the device
provides eight low skew outputs at speeds up to 160
MHz at 3.3 V. The MK2308-2 includes a bank of four
outputs running at 1/2X. In the zero delay mode, the
rising edge of the input clock is aligned with the rising
edges of all eight outputs. Compared to competitive
CMOS devices, the MK2308-2 has the lowest jitter.
Features
Packaged in 16-pin SOIC
Zero input-output delay
Four 1X outputs plus four 1/2X outputs
Output to output skew is less than 250 ps
Output clocks up to 160 MHz at 3.3 V
Ability to generate 2X the input
Full CMOS outputs with 18 mA output drive
capability at TTL levels at 3.3 V
Spread SmartTM technology works with spread
spectrum clock generators
Advanced, low power, sub micron CMOS process
Operating voltage of 3.3 V or 5 V
Block Diagram
FBIN
CLKIN
VDD
2
PLL
S2, S1 2
Control
Logic
/2
2
GND
CLKA1
CLKA2
CLKA3
BANK
A
CLKA4
CLKB1
CLKB2
CLKB3
BANK
B
CLKB4
MDS 2308-2 B
1
Revision 111103
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com




ICST

MK2308-2 Datasheet Preview

MK2308-2 Datasheet

ZERO DELAY LOW SKEW BUFFER

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Pin Assignment
CLKIN
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16 FBIN
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
16-pin (150 mil) SOIC
MK2308-2
ZERO DELAY, LOW SKEW BUFFER
Feedback Configuration Table
Feedback From
Bank A
Bank B
CLKA1:A4
CLKIN
2XCLKIN
CLKB1:B4
CLKIN/2
CLKIN
Output Clock Mode Select Table
S2 S1
Clocks A1:A4
Clocks B1:B4
Internet Generation
0 0 Tri-state (high impedance) Tri-state (high impedance)
None
01
Running
Tri-state (high impedance)
PLL
10
Running
Running
Buffer only (no zero delay)
11
Running
Running
PLL
Pin Descriptions
PLL Status
On
On
Off
On
Pin
Number
1
Pin
Name
CLKIN
Pin
Type
Input
Pin Description
Clock input. Connect to input clock source.
2 - 3 CLKA1:A4 Output Clock A bank of four outputs.
4
VDD
Power Power supply. Connect pin to same voltage as pin 13 (either 3.3 V or 5 V).
5
GND
Power Connect to ground.
6 - 7 CLKB1:B4 Output Clock B bank of four outputs. These are low skew divide by two of bank A.
8 S2 Input Select input 2. Selects mode for outputs per table above.
9 S1 Input Select input 1. Selects mode for outputs per table above.
10 - 11 CLKB1:B4 Output Clock B bank of four outputs. These are low skew divide by two of bank A.
12
GND
Power Connect to ground.
13
VDD
Power Power supply. Connect pin to same voltage as pin 4 (either 3.3 V or 5 V).
14 - 15 CLKA1:A4 Output Clock A bank of four outputs.
16
FBIN
Input Feedback input. Determines outputs per table above.
MDS 2308-2 B
2
Revision 111103
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com


Part Number MK2308-2
Description ZERO DELAY LOW SKEW BUFFER
Maker ICST
Total Page 5 Pages
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