MK2308-2 Datasheet | Renesas

Description The MK2308-2 is a low jitter, low skew, high performance Phase-Lock Loop (PLL) based zero delay buffer for high speed applications. Based on IDT’s proprietary low jitter PLL techniques, the device provides eight low skew outputs at speeds up to 133.3 MHz at 3.3 V. The MK2308-2 includes a bank of four outputs running at 1/2X. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of all eight outputs. pared to petitive CMOS devices, the MK2308-2 has the lowest jitter. Block Diagram Features - Packaged in 16-pin SOIC - Pb (lead) free package - Zero input-output delay - Four 1X outputs plus four 1/2X outputs - Output to output skew is less than 250 ps - Output clocks up to 133.3 MHz at 3.3 V - Ability to generate 2X the input - Full CMOS outputs with 18 m A output drive capability at TTL levels at 3.3 V - Spread Smart TM technology works with spread spectrum clock generators - Advanced, low power, sub micron CMOS process - Operating voltage of 3.3 V FBIN CLKIN VDD 2 CLKA1 CLKA2 CLKA3 BANK A CLKA4 /2 S2, S1 2 Control Logic 2 GND CLKB1 CLKB2 CLKB3 BANK B CLKB4 IDT™ ZERO DELAY, LOW SKEW BUFFER MK2308-2 REV E 051310 MK2308-2 ZERO DELAY, LOW SKEW BUFFER Pin Assignment CLKIN 1 CLKA1 2 CLKA2 3 VDD 4 GND 5 CLKB1 6 CLKB2 7 S2 8 16 FBIN 15 CLKA4 14 CLKA3 13 VDD 12 GND 11 CLKB4 10 CLKB3 9...