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8T74S208A-01 Datasheet

2.5V Differential LVDS Clock Divider and Fanout Buffer

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2.5V Differential LVDS Clock Divider and
Fanout Buffer
8T74S208A-01
REFER TO PCN# N1608-01, Effective Date November 18, 2016
FOR NEW DESIGNS USE PART NUMBER 8T74S208C-01
DATA SHEET
General Description
The 8T74S208A-01 is a high-performance differential LVDS clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T74S208A-01 is characterized to operate from a 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T74S208A-01 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I2C register. On
power-up, all outputs are disabled.
Features
One differential input reference clock
Differential pair can accept the following differential input levels:
LVDS, LVPECL, CML
Integrated input termination resistors
Eight LVDS outputs
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum input clock frequency: 1GHz
LVCMOS interface levels for the control inputs
Individual output enabled/ disabled by I2C interface
Output skew: 45ps (maximum)
Output rise/fall times: 370ps (maximum)
Low additive phase jitter, RMS: 96fs (typical)
Full 2.5V supply voltage
Outputs disable at power up
Lead-free (RoHS 6) 32-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
IN
nIN
50
fREF
÷1, ÷2,
÷4, ÷8
50
VT
FSEL[1:0] Pulldown (2)
2
SDA Pullup
SCL Pullup
ADR[1:0] Pulldown (2)
2
I2C
8
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
ADR1
GND
Q0
nQ0
Q1
nQ1
GND
VDDO
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
8T74S208A-01
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
FSEL0
GND
nQ7
Q7
nQ6
Q6
GND
VDDO
Q7 8T74S208A-01
nQ7
32-Lead VFQFN, 5mm x 5mm x 0.925mm
8T74S208A-01 REVISION 2 08/17/16
1 ©2016 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

8T74S208A-01 Datasheet

2.5V Differential LVDS Clock Divider and Fanout Buffer

No Preview Available !

8T74S208A-01 DATA SHEET
Pin Descriptions and Pin Characteristics
Table 1. Pin Descriptions1
Number
1
Name
ADR1
Type
Input
Pulldown
Description
I2C Address input. LVCMOS/LVTTL interface levels.
2
GND
Power
Ground pin.
3 Q0 Output
4 nQ0 Output
Differential output pair 0. LVDS interface levels.
5 Q1 Output
6 nQ1 Output
Differential output pair 1. LVDS interface levels.
7
GND
Power
Ground pin.
8
VDDO
Power
9 Q2 Output
10 nQ2 Output
Output supply pin.
Differential output pair 2. LVDS interface levels.
11 Q3 Output
12 nQ3 Output
Differential output pair 3. LVDS interface levels.
13 Q4 Output
14 nQ4 Output
Differential output pair 4. LVDS interface levels.
15 Q5 Output
16 nQ5 Output
Differential output pair 5. LVDS interface levels.
17
VDDO
Power
18
GND
Power
Output supply pin.
Ground pin.
19 Q6 Output
20 nQ6 Output
Differential output pair 6. LVDS interface levels.
21 Q7 Output
22 nQ7 Output
Differential output pair 7. LVDS interface levels.
23
GND
Power
Ground pin.
24
FSEL0
Input
Pulldown
Frequency divider select control. See Table 3A for function.
LVCMOS/LVTTL interface levels.
25
FSEL1
Input
Pulldown
Frequency divider select control. See Table 3A for function.
LVCMOS/LVTTL interface levels.
26 IN Input
Termination
27 VT Input
Non-inverting differential clock input. RT = 50termination to VT.
Input for termination. Both IN and nIN inputs are internally terminated 50
to this pin. See input termination information in the applications section.
28 nIN Input
Inverting differential clock input. RT = 50termination to VT.
29 VDD Power
Power supply pin.
30
SDA
I/O
Pullup
I2C Data Input/Output. Input. LVCMOS/LVTTL interface levels.
Output: open drain.
31
SCL
Input
Pullup
I2C Clock Input. LVCMOS/LVTTL interface levels.
32
ADR0
Input
Pulldown I2C Address input. LVCMOS/LVTTL interface levels.
NOTE 1: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
2.5V DIFFERENTIAL LVDS CLOCK DIVIDER AND FANOUT BUFFER
2
REVISION 2 08/17/16


Part Number 8T74S208A-01
Description 2.5V Differential LVDS Clock Divider and Fanout Buffer
Maker IDT
Total Page 19 Pages
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